The present invention relates to etch processes, materials and devices for plasma etching C-doped silicon oxide, such as oxidized organo silane compounds, to form dielectric materials and in particular to etch processes of these dielectric materials that provide improved etch selectivity to silicon oxide and organic photoresist.
A semiconductor device such as an IC (integrated circuit) generally has electronic circuit elements such as transistors, diodes and resistors fabricated integrally on a single body of semiconductor material. The various circuit elements are connected through conductive connectors to form a complete circuit which can contain millions of individual circuit elements. Advances in semiconductor materials and processing techniques have resulted in reducing the overall size of the IC circuit elements while increasing their number on a single body. Additional miniaturization is highly desirable for improved IC performance and cost reduction. Interconnects provide the electrical connections between the various electronic elements of an IC and they form the connections between these elements and the device""s external contact elements, such as pins, for connecting the IC to other circuits. Typically, interconnect lines form horizontal connections between electronic circuit elements while conductive via plugs form vertical connections between the electronic circuit elements, resulting in layered connections.
A variety of techniques are employed to create interconnect lines and via plugs. One such technique involves a process generally referred to as dual damascene, which includes forming a trench and an underlying via hole. The trench and the via hole are simultaneously filled with a conductor material, for example a metal, thus simultaneously forming an interconnect line and an underlying via plug. Examples of conventional dual damascene fabrication techniques are disclosed in Kaanta et al., xe2x80x9cDual Damascene: A ULSI Wiring Technologyxe2x80x9d, Jun. 11-12, 1991, VMIC Conference, IEEE, pages 144-152 and in U.S. Pat. No. 5,635,423 to Huang et al., 1997.
An example of a prior art dual damascene technique is illustrated in FIGS. 1A-1C, showing various IC structures. As depicted in FIG. 1A, a dielectric layer 110 is deposited on a semiconductor substrate 112. An etch mask 116, having a via pattern 118, is positioned on dielectric layer 110. A timed anisotropic etch is utilized to etch a hole 120 in layer 110 conforming to the via pattern. Mask 116 is subsequently replaced by mask 122 (FIG. 1B) having a trench pattern 124. A timed anisotropic etch is used to form trench 126 and to simultaneously deepen hole 120 to form via hole 128. This via hole can be etched to expose semiconductor substrate 112. Alternatively, the via hole can be over-etched partly into the substrate. As illustrated in FIG. 1C, the via hole and trench are then filled simultaneously with a suitable metal 130. Metal 130 thus forms a metallized interconnect line 132 and a via plug 134 that is in contact with semiconductor substrate 112. Additionally, a liner or barrier layer may be deposited inside the via hole and the trench prior to deposition of the interconnect metal and the via plug. The surface of layer 110 is planarized to remove excess metal 130 and to define interconnect line 132. Alternatively, metal etch-back can be utilized to define the line.
As described above in connection with etching hole 120 and trench 126, a timed etch procedure is required to form dual damascene structures exemplified by FIGS. 1A-1C. However, it is well known to those of ordinary skill in the art that timed etching techniques are not well suited for reliably forming holes of a predetermined depth. For example, a timed etch of holes across a semiconductor wafer can result in significant depth variations of holes across the wafer, particularly for 200 mm and 300 mm wafers. These depth variations can result in rejected semiconductor products that fail product specifications.
An example of prior art dual damascene that does not utilize a timed etch technique is shown in IC structures illustrated in FIGS. 2A-2C. As depicted in FIG. 2A, a first dielectric layer 210 is deposited on a semiconductor substrate 212. An etch stop layer 216, is deposited on first dielectric layer 210. A second dielectric layer 218 is deposited on etch stop 216, and an etch mask 220 is positioned on dielectric layer 218. Etch mask 220 is patterned (221) for etching a via hole. Second dielectric layer 218 is etched using a first anisotropic etch procedure, to form a hole 222 (FIG. 2A) conforming to the via pattern. This etching procedure is stopped at etch stop layer 216, by using an etch chemistry that is selective to the etch stop layer. Etch mask 220 is removed and another etch mask 224 (see, FIG. 2B) is positioned on second dielectric layer 218 such that it is patterned (226) for forming a trench. A second anisotropic etch procedure is used to etch trench 228 in layer 218. Simultaneously, hole 222 is extended to substrate 212, by etching through etch stop layer 216 and through first dielectric layer 210. In this dual damascene technique the first etch procedure has a greater selectivity to etch stop layer 216 than the second etch procedure. As shown in FIG. 2B, the second etch procedure results in forming trench 228 and via hole 230, that extends to semiconductor substrate 212. Mask 224 is removed, after which trench 228 and via hole 230 are simultaneously filled with a suitable conductive metal 232 (see, FIG. 2C) forming metallized line 234 and via plug 236 that contacts substrate 212. Excess metal 232 is removed from the surface of layer 218 to define line 234.
The techniques described in connection with FIGS. 2A-2C utilize an etch stop layer rather than a timed etch. Dielectric layers, such as layers 210 and 218 shown in FIGS. 2A-2C typically include materials that have a low dielectric constant such as silicon oxide and related silica glasses as well as dielectric polymeric materials. Etch stop layers include silicon nitrides such as Si3N4. The typical etch stop layer materials have a significantly higher dielectric constant than the materials utilized in the dielectric layers. It is known that the higher dielectric constant of these etch stop materials is disadvantageous because it can result in capacitive coupling between adjacent metal lines, that can lead to cross talk and/or RC (resistance coupling) delay that degrades the overall performance of the IC.
It is known to form dual damascene structures wherein one of the dielectric layers includes a SiOx material such as SiO2 or a silicon glass while the other dielectric layer comprises a dielectric material having a lower dielectric constant than SiOx. This combination can result in a combined dielectric structure having an improved, i.e. lower, dielectric constant as compared with a structure wherein both layers include SiOx. Dielectric materials having a lower dielectric constant than SiOx include C-doped silicon oxide materials, such as oxidized organo silane materials that are formed by partial oxidation of an organo silane compound, such that the dielectric material includes a carbon content of at least 1% by atomic weight, as described in U.S. Pat. Nos. 6,072,227 (Yau et al., 2000) and 6,054,379 (Yau et al., 2000) and U.S. Pat. application Ser. No. 09/553,461 which was filed Apr. 19, 2000, a continuation-in-part of U.S. Pat. No. 6,054,379. Commonly assigned U.S. Pat. Nos. 6,072,227 and 6,054,379, and U.S. Pat. application Ser. No. 09/553,461 are herein incorporated by reference in their entireties.
The oxidized organo silane materials, described in the ""227 and ""379 patents and the ""461 patent application, are formed by incomplete or partial oxidation of organo silane compounds generally including the structure: 
In this structure, xe2x80x94Cxe2x80x94 is included in an organo group and some Cxe2x80x94Si bonds are not broken during oxidation. Preferably xe2x80x94Cxe2x80x94 is included in an alkyl, such as methyl or ethyl, or an aryl, such as phenyl. Suitable organo groups can also include alkenyl and cyclohexenyl groups and functional derivatives. Preferred organo silane compounds include the structure SiHa(CH3)b(C2H5)c(C6H5)d, where a=1 to 3, b=0 to 3, c=0 to 3, d=0 to 3, and a+b+c+d=4, or the structure Si2He(CH3)f(C2H5)g(C6H5)h, where e=1 to 5, f=0 to 5, g=0 to 5, h=0 to 5, and e+f+g+h=6.
Suitable organo groups include alkyl, alkenyl, cyclohexenyl, and aryl groups and functional derivatives. Examples of suitable organo silicon compounds include but are not limited to:
Preferred organo silane compounds include but are not limited to: methylsilane; dimethylsilane; trimethylsilane; tetramethylsilane; dimethylsilanediol; diphenylsilane; diphenylsilanediol; methylphenylsilane; bis(methylsilano)methane; 1,2-bis(methylsilano)ethane; 1,3,5-trisilano-2,4,6-trimethylene; dimethyldimethoxysilane; diethyldiethoxysilane; dimethyldiethoxysilane; diethyldimethoxysilane; hexamethyldisiloxane; octamethylcyclotetrasiloxane; and fluorinated derivatives thereof. The most preferred organo silane compounds include methyl silane and trimethyl silane.
The organo silane compounds are oxidized during deposition by reaction with oxygen (O2) or oxygen containing compounds such as nitrous oxide (N2O) and hydrogen peroxide (H2O2), such that the carbon content of the deposited film is from 1% to 50% by atomic weight, preferably about 20%. The oxidized organo silane layer has a dielectric constant of about 3.0. Carbon, including some organo functional groups, remaining in the oxidized organo layer contributes to low dielectric constants and good barrier properties providing a barrier that inhibits for example diffusion of moisture or metallic components. These oxidized organo silane materials exhibit good adhesion properties to silicon oxide and silicate glass as well as typical dielectric materials employed in IC structures. The above described oxidized organo silanes include BLACK DIAMOND(trademark) technology, available from Applied Materials, Inc. located in Santa Clara, Calif.
Plasma conditions for depositing a layer of the oxidized organo silane material having a carbon content of at least 1% by atomic weight, include a high frequency RF power density from about at least 0.16 W/cm2 and a sufficient amount of organo silane compound with respect to the oxidizing gas to provide a layer with carbon content of at least 1% by atomic weight. When oxidizing organo silane materials with N2O, a preferred high frequency RF power density ranges from about 0.16 W/cm2 to about 0.48 W/cm2. These conditions are particularly suitable for oxidizing CH3xe2x80x94SiH3 with N2O. Oxidation of organo silane materials such as (CH3)3xe2x80x94SiH with O2 is preferably performed at a high frequency RF power density of at least 0.3 W/cm2, preferably ranging from about 0.9 W/cm2 to about 3.2 W/cm2. Suitable reactors for depositing this material include parallel plate reactors such as those described in the ""379 and ""227 patents. As shown in the ""227 and ""379 patents and in the ""461 application, the oxidized organo silane materials including at least 1% of carbon can be utilized in multi-layered structures such as are used, for example, in fabricating dual damascene integrated circuit structures.
A conventional etch chemistry for silicon oxide was used to etch a trench through a layer of partially oxidized organo silane material that was deposited on a layer of conventional SiO2 as illustrated in FIGS. 3A, 3B and 5. As depicted in FIG. 3A, a layer 310 of silicon dioxide was deposited on a semiconductor substrate (not shown) by PECVD (plasma enhanced chemical vapor deposition) using TEOS (tetraorthosilicate) and ozone reactants. Methods and technologies for depositing silicon dioxide such as layer 310 are well known to those of ordinary skill in the art, see for example U.S. Pat. No. 5,362,526 (Wang et al., 1994). A layer 312 of partially oxidized CH3SiH3 was deposited on layer 310, using N2O oxidizing gas in argon inert carrier gas, and employing PECVD layer deposition technology as described in the ""227 and ""379 patents. An ARC (antireflective coating) 313 including SiON was then deposited on layer 312. Subsequently, a layer 314 of deep U.V. organic photoresist was deposited on layer 313 and a trench mask 316 was developed in resist layer 314.
A trench 318 was anisotropically etched in ARC layer 313 and in oxidized organo silane layer 312, using etch mask 316, see FIG. 3B. Trench 318 etching was performed in an IPS (inductive plasma source) etch reactor available from Applied Materials, Inc. of Santa Clara, Calif. In this type of reactor a HDP (high density plasma) is generated wherein the plasma is independent from the biasing of the pedestal supporting the semiconductor wafer containing structures such as the structure illustrated in FIG. 3A.
The IPS etch reactor utilized in etching trench 318, shown in FIG. 3B, is schematically illustrated in FIG. 4. A semiconductor wafer 440 is supported on a cathode pedestal 442, that is supplied with RF (radio frequency) power from a first RF power supply 444. A silicon ring 446 surrounds the pedestal 442 and is controllaby heated by an array of heater lamps 448. A grounded silicon wall 450 surrounds the plasma processing area. A silicon roof 452 overlies the plasma processing area, and lamps 454. Water cooling channels 456 control the roof temperature. The temperature-controlled silicon ring 486, and the silicon roof 452, can be used to scavenge fluorine from the fluorocarbon or other fluorine-based plasma. Processing gas is supplied from one or more gas feeds 454 through a bank of mass flow controllers 456. Alternatively, a top gas fed may be formed as a small showerhead in the center of the silicon roof 452. An unillustrated vacuum pumping system connected to a pumping channel 458 around the lower portion of the chamber maintains the interior of the chamber at a preselected pressure. A system controller 460 controls the operation of the reactor and its auxiliary equipment.
In the used configuration, the silicon roof 452 is grounded, see FIG. 4. The semiconductor resistivity and thickness of roof 452 are chosen to pass generally axial RF magnetic fields produced by an inner inductive coil stack 466 and an outer inductive coil stack 468 powered by respective RF power supplies 470 and 472. Alternatively, a single RF power supply may be used in conjunction with a selectable power splitter. Other coil configurations are possible, for example, as in the TCP reactor having a flat, spiral inductive coil overlying the roof 452.
The system controller 460 controls the mass flow controllers 456, the heater lamps 448, 454, the supply of chilled water to the cooling channels 456, the throttle valve to the vacuum pumps, and the power supplies 444, 470 and 472. All these regulated functions control the etching chemistry in conformance to the processing conditions to be described in connection with FIGS. 3A, 3B and 5, and in Table A. The process recipe can be stored in the controller 460 in magnetic, optical, or semiconductor memory, as is well known in the art, and the controller 460 reads the recipe from a recording medium inserted into it. Recipes can be provided on magnetic media such as floppy disks or optical media such as CDROMs, that can then be read into controller 460.
Inductively coupled plasma reactors, such as shown in FIG. 4, are adapted to provide different amounts of power to inductive coils 466 and 468, and to capacitive pedestal 442. The inductive power creates a plasma source region located in large part remotely from the wafer 440 while the capacitive power controls the plasma sheath adjacent to the wafer 440 and thus determines the DC bias across the sheath at the wafer 440. The source power can be raised to increase the etching rate and control the number and type of excited radicals while the bias power can be varied to cause ions to be accelerated across the plasma sheath with either high or low energy and to then strike the wafer 440 with the selected energy.
The etch parameters for etching trench 318 (FIG. 3B) using C4F8/Ar chemistry are shown in Table A. These parameters are typical of conventional etch parameters for IPS etching of silicon oxide containing dielectric layers such as are employed in IC structures.
A typical example of a trench etch of the structure shown in FIG. 3A, using the etch reactor exemplified in FIG. 4 and the etch parameters shown in Table A, is depicted in the cross sectional view of FIG. 3B. As shown in FIG. 3B, etch front 320 does not exhibit high SiO2 etch selectivity under these etching conditions since the trench etch progressed partly into silicon dioxide layer 310 without removing all of the oxidized organo silane material from the bottom of trench 318. It is therefore difficult to achieve an effective etch stop with SiO2, when etching a dielectric material including at least 1% of carbon that is formed by a partially oxidized organo silane material, and using conventional etch chemistry such as C4F8 g/Ar chemistry according to the parameters of Table A. It has also been observed that micro trenches are likely to be formed at the interface between the oxidized organo silane layer and the underlying silicon oxide layer when a trench for depositing an interconnect line is etched through the oxidized organo silane layer employing a conventional etch recipe for etching silicon oxide.
FIG. 5 illustrates another example of using C4F8/Ar chemistry for etching a structure including SiO2 layer 510, oxidized organo silane material layer 512 and photoresist layer 514. Layers 510, 512, 513 and 514 of FIG. 5 correspond to layers 310, 312, 313 and 314 respectively illustrated in FIG. 3A. The etch parameters for etching this structure are shown in Table A. Returning to FIG. 5, etch front 520 shows that SiO2 does not provide an effective etch stop for this etching process of a dielectric material including at least 1% of carbon that is formed by a partially oxidized organo silane material.
A substantially flat etch front is highly desirable when etching for example trenches and via holes in dielectric layers for fabricating IC structures. The degree of flatness of an etch front of a typical cross section can be expressed as an EFF (etch front flatness) that can be calculated for an etch profile such that EFF equals the following ratio: delta etch front/maximum etch depth. xe2x80x9cDelta etch frontxe2x80x9d denotes the height difference between the highest and lowest points of the edge front, while xe2x80x9cmaximum etch depthxe2x80x9d constitutes the etch depth from the top of the dielectric layer to the bottom of lowest point of the edge front. The xe2x80x9cdelta etch frontxe2x80x9d and xe2x80x9cmaximum etch depthxe2x80x9d are both expressed in the same units. For example, the etch profile of trench 318 (FIG. 3B) as shown in FIG. 6 exhibits a delta etch front D1=87 nm and a maximum etch depth M1=382 nm, resulting in an EFF of 0.23, wherein the maximum etch depth is measured from the top of layer 312 to the bottom of the lowest point of edge front 320. Measurements D1 and M1 were conducted on an SEM (scanning electron micrograph) (not shown) of FIG. 6. Trench 318 was fabricated at a width of about 500 nm and a depth of about 330 nm
As shown in FIGS. 3A and 3B, the resist layer is partly stripped following trench etching.
Silicon nitrides are known to have high selectivity to etch chemistries that are used for etching silicon oxides, such as the C4F8/Ar etch chemistry shown in Table A. It would thus be possible to use an etch chemistry such as C4F8/Ar for etching a top layer of a partially oxidized organo silane when a nitride etch stop is deposited between this top layer and an underlying layer of silicon oxide. However, the use of a nitride etch stop results in less favorable dielectric properties as described in connection with FIGS. 2A-2C, thus partly negating the advantages of the low dielectric constant of the partially oxidized organo silane material.
Accordingly, the need exists for etch chemistries for C-doped silicon oxide such as partially oxidized organo silane materials including at least 1% of carbon, that provide improved etch selectivity to silicon oxide.
The present invention provides novel methods and techniques for etching C-doped silicon oxide, such as partially oxidized organo silane materials, that overcome the prior art etching problems described above.
In one embodiment of the present invention a novel etch technique is employed for etching a layer of C-doped silicon oxide, such as a partially oxidized organo silane material including at least 1% of carbon by atomic weight. This technique utilizing CH2F2/Ar chemistry at low bias and low pressure.
In another embodiment of the present invention a layer of partially oxidized organo silane material including at least 1% of carbon by atomic weight, was deposited on a layer of silicon oxide. An etch pattern was anisotropically etched through the layer of partially oxidized organo silane material, employing the novel etch technique. High SiO2 etch selectivity and a substantially flat etch front were obtained, having an etch front flatness no greater than 0.1. Also, the novel etch technique resulted in improved selectivity to organic photoresist.
In an additional embodiment of the present invention, a layer of C-doped silicon oxide is deposited on a layer of silicon oxide that is formed on a substrate. A via pattern is etched sequentially through the layers of C-doped silicon oxide and silicon oxide. Subsequently, the novel etch procedure is employed for etching a trench through the layer of C-doped silicon oxide overlaying the hole formed by etching the via pattern.
In another embodiment of the present invention a layer of silicon nitride was deposited on a semiconductor substrate. This was followed by the deposition of layers of adhesion promoter, silicon oxide, adhesion promoter, oxidized organo silane material and photoresist. A via etch pattern was developed in the resist. The via etch pattern was then anisotropically etched to expose the silicon nitride layer. A trench etch pattern was developed overlaying the hole. Employing the novel etch technique, the trench pattern was anisotropically etched through the oxidized organo silane layer and the underlying layer of adhesion promoter, thus forming a trench on an underlying via hole. The bottom of the trench exposed the silicon oxide layer and it was observed that a substantially flat etch front was obtained at the bottom of the etch. The novel technique is not selective to silicon nitride. As a result, trench etching opens the silicon nitride layer at the bottom of the via hole. However, this technique utilizes a bias that is too low to cause copper sputter of a copper line that is exposed at the bottom of the via hole. The trench and via hole can simultaneously be filled with a conductive material to form a dual damascene structure. Alternatively, the via and trench can be lined with a liner such as a barrier liner or adhesive layer prior to simultaneously filling the via hole and trench with a conductive material. Additionally, silicon nitride exposed at the bottom of the hole can be protected from the trench etching process by partly filling the bottom of the via hole with an organic ARC (antireflective coating) material. It is also contemplated to protect the silicon nitride at the bottom of the hole by providing photoresist material in the hole, prior to etching the trench.
In additional embodiments novel IC structures were formed including a metallizing layer of partially oxidized organo silane material, deposited on a layer of silicon oxide. One or more cavities were etched in the metallization layer utilizing the novel etch technique, such that a substantially flat etch front was obtained.
In a further embodiment of the present invention, a manufacturing system is provided for forming fabricated structures, such as the IC structures of the present invention. This system includes a controller, such as a computer, that is adapted for interacting with a plurality of fabrication stations. Each of these fabrication stations performs a processing step that is utilized to fabricate the IC structures. Operative links provide connections between the controller and the manufacturing stations. A data structure, such as a computer program, causes the controller to control the processing steps which are performed at the fabrication stations.